Tonal Behavior Analysis of an Adaptive Second-Order Sigma-Delta Modulator

This paper analyzes the tonal behavior of an adaptive second-order sigma-delta modulator, which was developed and published by the same authors. Idle channel tones, caused by non-white quantization error, is not desirable in applications where the human ear is the end receiver. Besides their relatively small magnitude tones in the baseband, most sigma-delta modulators produce high-powered tones near fs/2. It is a more serious problem because the clock noise near fs/2 can couple these tones down into the baseband. Various simulations show that the more randomized nature of the aforementioned adaptive architecture makes it more advantageous in tonal behavior, particularly attractive in that it significantly reduces the dominant tone near fs/2, which can not be reduced by dithering in a standard second order single-bit modulator. With comparison to the standard second-order sigma-delta modulators, the results are illustrated in both frequency and time domains

A 1.2 V, 38 micro\u3ci\u3eW \u3c/i\u3eSecond-Order DeltaSigma Modulator with Signal Adaptive Control Architecture

A 1.2 V, 38 μW second-order ΔΣ modulator (ΔΣM) with a Signal Adaptive Control (SAC) architecture is fabricated in a 0.35 μm standard CMOS technology (Vt,n = 0.6V, Vt,p = -0.8V). This modulator achieves 75 dB dynamic range and 63 dB of peak SNDR at 6.8kHz Nyquist rate and an oversample ratio of 64. The proposed architecture effectively reduces the power dissipation while keeping the modulator performance almost unchanged

An Extended Frequency Range CMOS Voltage-Controlled Oscillator

This paper presents an extended frequency range CMOS monolithic voltage-controlled oscillator (VCO) design. A negative feedback control algorithm is used to automatically adjust the VCO range according to the control voltage. Based on this analog feedback control algorithm, the VCO achieves a wide range without any pre-register settings. Low phase noise is achieved by using both coarse control and fine control in VCO. A 600 MHz to 3.3 GHz monolithic CMOS PLL based on this wide range and low phase noise VCO has been fabricated in TSMC 0.18 μm, 1.8V CMOS technology and is used in many different applications such as FC, GE, and SONET etc

A Fully Integrated CMOS Phase-Locked Loop With 30MHz to 2GHz Locking Range and ±35 ps Jitter

A fully integrated phase-locked loop (PLL) fabricated in a 0.24μm, 2.5v digital CMOS technology is described. The PLL is intended for use in multi-gigabit-per-second clock recovery circuits in fiber-optic communication chips. This PLL first time achieved a very large locking range measured to be from 30MHz up to 2GHz in 0.24μm CMOS technologies. Also it has very low peak-to-peak jitter less than ±35ps at 1.25GHz output frequency

Fully Integrated CMOS Phase-Locked Loop With 30MHz to 2GHz Locking Range and +-35ps Jitter

A fully integrated phase-locked loop (PLL) fabricated in a 0.24 micrometer, 2.5v digital CMOS technology is described. The PLL is intended for use in multi-gigabit-per-second clock recovery circuits in fiber-optic communication chip. This PLL first time achieved a very large locking range measured to be from 30MHz up to 2GHz in 0.24 micrometer CMOS technology. Also it has very low peak-to-peak jitter less than +-35ps at 1.25GHz output frequency

Analysis of Clock Buffer Phase Noise

This paper presents a phase noise model for clock buffers. The model can be used to predict the phase noise introduced by clock buffers and to gain insight into phase noise transfer mechanisms in clock buffers. Based on the models, techniques for low phase noise clock buffer design are derived. The analytical results presented here have good agreement with simulation and measurement results

Design of analog integrated circuits and system

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